1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating NOR type memory cells of a nonvolatile memory device such as an EEPROM or a flash memory device.
2. Description of the Related Art
Recently, nonvolatile memory devices such as EEPROMs or flash memories have been used in all domestic electronic appliances, easily available in the surroundings, such as digital cellular phones, digital set-top boxes, digital cameras, personal computers, modems, facsimiles, digital camcorders, and DVD players. In order to achieve a miniature and high performance of such domestic electronic appliances, active research is being made for a high integration of EEPROMs or flash memories.
As well known, the memory cell structure of such an EEPROM or flash memory is of a NOR type or of a NAND type.
Referring to FIG. 1a, a NOR type memory cell structure is illustrated. In the NOR type memory cell structure of FIG. 1a, each memory cell is connected at a drain electrode D thereof to a bit lines BL, at a gate electrode G thereof, that is, a control gate cg thereof, to a word line WL, and at a source electrode S thereof to a source electrode line SL. In FIG. 1a, the reference character xe2x80x9cfgxe2x80x9d denotes a floating gate electrode of each memory cell.
Such a NOR type memory cell structure has an advantage in that it has a high operating speed. However, this NOR type memory cell structure has a drawback in that it is difficult to achieve an improvement in integration because each memory cell has a contact. In other words, each memory cell of the NOR type memory cell structure is connected at its drain electrode D to an associated bit line BL, and at its source electrode S to an associated source electrode line SL. For this reason, the memory cell must have a certain contact area for providing contacts for connecting to the bit and source electrode lines. As a result, it is difficult to achieve an improvement in integration.
Referring to FIG. 1b, a NAND type memory cell structure is illustrated. In the NAND type memory cell structure of FIG. 1b, 8 memory cells are connected to a first bit line BL1 to which a pair of select transistors TR1 and TR2 are also coupled. Another 8 memory cells are connected to a second bit line BL2 to which a pair of select transistors TR3 and TR4 are also coupled. Opposite to the first and second bit lines BL1 and BL2, a source electrode line SL is connected to respective source electrodes S of the select transistors TR2 and TR4. By this arrangement, the 16 memory cells form a unit memory. Such a NAND memory cell structure has an advantage in that it can easily achieve an improvement in integration because it is unnecessary to provide contacts at all memory cells. In other words, in this NAND memory cell structure, each bit line BL1 or BL2 is connected only to the drain electrode D of a first one of the associated 8 memory cells. The connections of the remaining 7 memory cells to the associated bit line are achieved in that those memory cells are connected in series to the first memory cell. The source electrode line SL is connected to the source electrode S of the last one of the 8 memory cells. By virtue of such an arrangement, the area required for the connection of the memory cells to the bit and source electrode lines is minimized. Accordingly, it is easy to achieve an improvement in integration.
However, this NAND type memory cell structure additionally requires 4 select transistors for every 16 memory cells. For this reason, there is a drawback of a low operating speed.
Accordingly, current domestic electronic appliances mainly use products of the NOR type memory cell structure because the NOR type memory cell structure has a high operating speed, as compared to the NAND type memory cell structure, even though it has a drawback in that it is difficult to achieve a high integration, as compared to the NAND type memory cell structure.
FIG. 2 is a plan view illustrating masks mainly used in the manufacture of NOR type memory cells in accordance with a conventional method. In FIG. 2, the reference numeral xe2x80x9c202xe2x80x9d denotes an isolation mask, xe2x80x9c206xe2x80x9d a control gate electrode mask, and xe2x80x9c208xe2x80x9d a contact mask. The reference character xe2x80x9cAxe2x80x9d denotes a unit memory cell.
A source electrode line is formed by a diffusion region formed in a semiconductor substrate. Respective source electrodes of unit memory cells aligned with one another are interconnected together by the source electrode line. The isolation mask 202 is designed in such a fashion that it overlaps with the control gate electrode mask 206 at desired portions thereof. In FIG. 2, the reference character xe2x80x9cbxe2x80x9d denotes the overlap width (size) between the isolation mask 202 and the control gate electrode mask 206.
In such a conventional NOR type memory cell design, however, it is necessary to provide an increased cell area because there is an overlapping area between the isolation mask 202 and the control gate electrode mask 206. Due to such an increased cell area, it is difficult to achieve an improvement in integration.
Therefore, an object of the invention is to provide a method for fabricating NOR type memory cells of a nonvolatile memory device, which is capable of achieving an improvement in integration.
In accordance with the present invention, this object is accomplished by providing method for fabricating NOR type memory cells of a nonvolatile memory device, comprising the steps of: forming a floating gate insulating film, a floating gate electrode, a control gate insulating film, a control gate electrode, and an insulating film sequentially stacking in the shape of pattern on each of memory cell regions of a semiconductor substrate defined by an isolation film; forming a source electrode and a drain electrode in portions of the semiconductor substrate exposed at both sides of the gate electrode, respectively; forming a first etching barrier film on the resultant; forming a first interlayer insulating film on the first etching barrier film in a planarized fashion; etching a desired portion of the first interlayer insulating film so as to form first contact hole exposing the source and drain electrodes, respectively; forming a first conductive film in a planarized fashion on the resultant so as to bury the first contact hole; etching the first conductive film so as to form a source electrode line contacting the source electrode and a contact plug contacting the drain electrode; forming a second etching barrier film on the resultant; forming a second interlayer insulating film in a planarized fashion on the second etching barrier film; etching a desired portion of the second insulating film so as to form second contact hole exposing the contact plug; and forming a bit line connected to the contact plug via the second contact hole on the second interlayer insulating film.